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NXP Semiconductors /LPC176x5x /SYSCON /DMACREQSEL

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Interpret as DMACREQSEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMASEL08)DMASEL08 0 (DMASEL09)DMASEL09 0 (DMASEL10)DMASEL10 0 (DMASEL11)DMASEL11 0 (DMASEL12)DMASEL12 0 (DMASEL13)DMASEL13 0 (DMASEL14)DMASEL14 0 (DMASEL15)DMASEL15 0RESERVED

Description

Selects between alternative requests on DMA channels 0 through 7 and 10 through 15

Fields

DMASEL08

Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected.
DMASEL09

Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected.
DMASEL10

Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected.
DMASEL11

Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected.
DMASEL12

Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected.
DMASEL13

Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected.
DMASEL14

Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected.
DMASEL15

Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data